A 0.15 /spl mu/m CMOS foundry technology with 0.1 /spl mu/m devices for high performance applications

Author

Diaz, C.H. ; Chang, M. ; Chen, W. ; Chiang, M. ; Su, H. ; Chang, S. ; Lu, P. ; Hu, C. ; Pan, K. ; Yang, C. ; Chen, L. ; Su, C. ; Wu, C. ; Wang, C.H. ; Wang, C.C. ; Shih, J. ; Hsieh, H. ; Tao, H. ; Jang, S. ; Yu, M. ; Shue, S. ; Chen, B. ; Chang, T. ; Hou,

Author_Institution

Taiwan Semicond. Manuf. Co., Taiwan

fYear

2000

fDate

13-15 June 2000

Firstpage

146

Lastpage

147

Abstract

This paper describes a leading-edge 0.15 /spl mu/m CMOS logic foundry technology family. Advanced core devices using 20 /spl Aring/ oxides for 1.2-1.5 V operation (L/sub G min/=0.1 /spl mu/m) support high-performance CPU and graphics applications. The technology supports also low-standby power applications with 26 /spl Aring/ oxide for 1.5 V operation. Periphery circuitry for 2.5 or 3.3 V compatibility use dual 50 or 65 /spl Aring/ gate oxides respectively. AlCu with low-k (FSG) is used for the seven-level metal interconnect system with extremely tight pitch (0.39 /spl mu/m for M1 and 0.48 /spl mu/m for intermediate levels). The aggressive design rules and border-less contacts/vias render an embedded (synchronous cache) 6T SRAM cell of 3.42 /spl mu/m/sup 2/ demonstrated in a 2Mb vehicle with very high yield. The overall process reliability is also shown to meet standard industry requirements.

Keywords

CMOS memory circuits; SRAM chips; application specific integrated circuits; integrated circuit interconnections; integrated circuit reliability; integrated circuit yield; low-power electronics; ultraviolet lithography; 0.1 micron; 0.15 micron; 1.2 to 1.5 V; 20 angstrom; CMOS foundry technology; DUV gate patterning; advanced core devices; attenuated phase shift; borderless contacts/vias; design rules; dual gate oxides; embedded SRAM cell; graphics applications; high performance applications; high-performance CPU; intrinsic TDDB; low-k dielectric; low-standby power applications; optical proximity correction; overall process reliability; process integration; seven-level metal interconnect; synchronous cache; technology scaling; very high yield; Application specific integrated circuits; CMOS technology; Delay; Foundries; Integrated circuit interconnections; Leakage current; Logic devices; Manufacturing industries; Pulp manufacturing; Semiconductor device manufacture;

fLanguage

English

Publisher

ieee

Conference_Titel

VLSI Technology, 2000. Digest of Technical Papers. 2000 Symposium on

Conference_Location

Honolulu, HI, USA

Print_ISBN

0-7803-6305-1

Type

conf

DOI

10.1109/VLSIT.2000.852803

Filename

852803