A novel logic compatible gain cell with two transistors and one capacitor

Summary form only given. In consumer electronics, cost-effective embedded technology is an important subject. We propose a novel, cost-effective gain cell for memory embedded in logic LSIs. The new cell consists of two conventional bulk transistors and one MOS capacitor. It can be fabricated using the pure logic process with a few additional process steps. The fabrication cost of this cell is lower than that of DRAM or SRAM at a memory density in the 1/spl sim/100 Mbit range.