Modeling gate and substrate currents due to conduction- and valence-band electron and hole tunneling [CMOS technology]

A model is proposed to quantify the tunneling currents through ultra-thin gate oxides. With a proper set of effective mass and barrier height, this new model can accurately predict the gate and substrate currents and all the subcomponents in dual-gate CMOS devices. This model can also be employed to extract T/sub ox/ for thin oxide from I-V data with 0.1/spl Aring/ sensitivity, where C-V extraction can be difficult or impossible.