DocumentCode
2163229
Title
A novel low-power building block CMOS cell for adders
Author
Shams, Ahmed M. ; Bayoumi, Magdy A.
Author_Institution
Center for Adv. Comput. Studies, Southwestern Louisiana Univ., Lafayette, LA, USA
Volume
2
fYear
1998
fDate
31 May-3 Jun 1998
Firstpage
153
Abstract
A new low-power, high-speed CMOS 1-bit full adder cell is presented. It is based on recent designs of XOR and XNOR gates, and pass-transistors, it has 16 transistors. This cell has been compared to two widely used efficient adder cells; the transmission function full adder cell (16 transistors), and the low power adder cell (14 transistors). The new cell has no short circuit power and lower dynamic power, because of less number and magnitude of circuit capacitances. It consumes up to 21% less power than the other two cells, while it is 12% to 20% faster. A comparative analysis (using Magic and Hspice) for 8-bit ripple-carry and carry-select adders shows that the adders based on the new cell can save up to 29% of power consumption
Keywords
CMOS logic circuits; SPICE; adders; 8 bit; Hspice; Magic; XNOR gate; XOR gate; carry-select adder; dynamic power; high-speed full adder; low-power building block CMOS cell; pass transistor; ripple-carry adder; short circuit power; simulation; Adders; Arithmetic; Capacitance; Energy consumption; Leakage current; Power supplies; Short circuit currents; Switching circuits; Very large scale integration; Voltage;
fLanguage
English
Publisher
ieee
Conference_Titel
Circuits and Systems, 1998. ISCAS '98. Proceedings of the 1998 IEEE International Symposium on
Conference_Location
Monterey, CA
Print_ISBN
0-7803-4455-3
Type
conf
DOI
10.1109/ISCAS.1998.706864
Filename
706864
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