CMP-free and CMP-less approaches for multilevel Cu/low-k BEOL integration

Author

Tsai, M.H. ; Chou, S.W. ; Chang, C.L. ; Hsieha, C.H. ; Lin, M.W. ; Wu, C.M. ; Shue, W.S. ; Yu, D.C. ; Liang, M.S.

Author_Institution

Taiwan Semicond. Manuf. Co., Hsin-Chu, Taiwan

fYear

2001

fDate

2-5 Dec. 2001

Abstract

A CMP-free process by electropolishing (EP) the planar contact plating (CP) Cu film and TaN dry etching which eliminate the stress induced peeling during CMP was demonstrated. Nanometer smoothness and a highly <111> texture of Cu can be achieved by optimizing the EP process. A 4-level Cu/low-k interconnect with CMP-less process was demonstrated with excellent yield. This process improves the throughput on ECP and CMP by two and has less dishing.

Keywords

copper; dielectric thin films; electrolytic polishing; integrated circuit interconnections; sputter etching; tantalum compounds; 4-level Cu/low-k interconnects; CMP-free process; CMP-less process; Cu-TaN; RIE; TaN dry etching; electropolishing; global planarization; multilevel Cu/low-k BEOL integration; nanometer smoothness; planar contact plating Cu film; reactive ion etching; stress induced peeling elimination; trench patterned wafers; Adhesives; Degradation; Delay; Dielectric losses; Dry etching; Logic; Performance evaluation; Stress; Surfaces; Throughput;

fLanguage

English

Publisher

ieee

Conference_Titel

Electron Devices Meeting, 2001. IEDM '01. Technical Digest. International

Conference_Location

Washington, DC, USA

Print_ISBN

0-7803-7050-3

Type

conf

DOI

10.1109/IEDM.2001.979408

Filename

979408