A 60 ns access 32 kByte 3-transistor flash for low power embedded applications

Author

Ikehashi, T. ; Noda, J. ; Imamiya, K. ; Ichikawa, M. ; Iwata, A. ; Futatsuyama, T.

Author_Institution

ULSI Device Eng. Lab., Toshiba Corp., Yokohama, Japan

fYear

2000

fDate

15-17 June 2000

Firstpage

162

Lastpage

165

Abstract

In this paper, we present a new memory, 3-transistor flash (3-Tr), which is suited to the embedded application. The memory cell has inherited low power the erase/program characteristic of the NAND flash. The cell size of the 32kByte 3-Tr flash, fabricated in a 0.4um NAND flash technology, is 4.36 /spl mu/m/sup 2/. This is about 1/8 of the EEPROM cell size having the same design rule. We also propose two circuit technologies, a low power sensing scheme and a double stage boosting scheme (DSB). The sense scheme aims to reduce the power of the read operation without degrading access time. DSB, on the other hand, improves the power consumption property of the word line (WL) decoder during the program mode. It is also immune to a decrease of the supply voltage Vdd.

Keywords

Flash memories; Integrated memory circuits; Memory architecture; NAND circuits; 0.4 micron; 3-Tr; 3-transistor flash; 32 kByte; 60 ns; NAND flash; access time; cell size; circuit technologies; double stage boosting scheme; low power embedded applications; low power sensing scheme; memory cell; power consumption property; program mode; read operation; sense scheme; supply voltage Vdd; word line decoder; Differential amplifiers; EPROM; Energy consumption; Laboratories; Large scale integration; Latches; Power engineering and energy; Pulse amplifiers; Ultra large scale integration; Voltage;

fLanguage

English

Publisher

ieee

Conference_Titel

VLSI Circuits, 2000. Digest of Technical Papers. 2000 Symposium on

Conference_Location

Honolulu, HI, USA

Print_ISBN

0-7803-6309-4

Type

conf

DOI

10.1109/VLSIC.2000.852879

Filename

852879