DocumentCode
2163997
Title
Yield considerations in the design of WASP3
Author
Bolouri, Hamid ; Lea, R. Mike
Author_Institution
Hatfield Polytech., UK
fYear
1991
fDate
29-31 Jan 1991
Firstpage
170
Lastpage
177
Abstract
Addresses yield modeling considerations in the development of the WASP (WSI associative string processor) architecture, floor plan, and defect-tolerance strategy. A fully parameterized, detailed yield model for WASP devices is presented, and the implications of various design options for device yield are analyzed. The WASP architecture has been shown to be capable of yields well in excess of the target of 50% for 8192-APE WASP devices
Keywords
VLSI; fault tolerant computing; parallel architectures; 8192-APE; WASP architecture; WASP3; WSI associative string processor; defect-tolerance strategy; floor plan; yield modeling; Application specific processors; Associative processing; Chromium; Circuit faults; Circuit testing; Fabrication; Logic testing; Redundancy; Ultra large scale integration; Wafer bonding;
fLanguage
English
Publisher
ieee
Conference_Titel
Wafer Scale Integration, 1991. Proceedings., [3rd] International Conference on
Conference_Location
San Francisco, CA
Print_ISBN
0-8186-9126-3
Type
conf
DOI
10.1109/ICWSI.1991.151712
Filename
151712
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