A 1.29 um/sup 2/ full CMOS ultra-low power SRAM cell with 0.12 um spacer-on-stopper (SOS) CMOS technology

Author

Sung-Bong Kim ; Do-Hyung Kim ; Kwang-Ok Koh ; Yong Park ; Han-Shin Lee ; Jai-Kyun Park ; Joon-Yong Joo ; Jin-Ho Kim ; Byung-Joon Hwang ; Moo-Sung Kim ; Ji-Young Lee ; Suk-Joo Lee ; Seung-Hyun Park ; Jung-In Hong ; Moon-Yong Lee

Author_Institution

TD Team, Samsung Electron. Co. Ltd., Gyungki-Do, South Korea

fYear

2001

fDate

2-5 Dec. 2001

Abstract

We have developed a 1.29 um2 full CMOS SRAM cell for low power applications, which is the world-smallest one by using 0.12 um single gate CMOS technology and optical enhancement techniques for extending use of 248 nm KrF lithography. It includes (1) 0.28 um pitch contacts formed by aerial image controlled patterns on phase shift mask (PSM) and photo resist flow, (2) gate patterns with 0.24 um pitch, (3) 0.13 um buried channel pMOS, and (4) spacer-on-stopper (SOS) MOSFET structure for expanding contact area and reducing band-to-band tunneling leakage.

Keywords

CMOS memory circuits; SRAM chips; low-power electronics; phase shifting masks; photoresists; ultraviolet lithography; 0.12 micron; 248 nm; CMOS ultra-low power SRAM cell; KrF lithography; aerial image control; band-to-band tunneling leakage; buried channel pMOS; contact area; gate pattern; optical enhancement technique; phase shift mask; photoresist flow; single gate technology; spacer-on-stopper MOSFET; Bridges; CMOS technology; Contacts; Etching; Leakage current; Lithography; Random access memory; Resists; Space technology; Tunneling;

fLanguage

English

Publisher

ieee

Conference_Titel

Electron Devices Meeting, 2001. IEDM '01. Technical Digest. International

Conference_Location

Washington, DC, USA

Print_ISBN

0-7803-7050-3

Type

conf

DOI

10.1109/IEDM.2001.979478

Filename

979478