A 0.13 /spl mu/m full metal embedded DRAM technology targeting on 1.2 V, 450 MHz operation

Author

Arai, S. ; Sakoh, T. ; Kitamura, T. ; Shirai, H. ; Aoki, Y. ; Sakao, M. ; Inoue, K. ; Takeuchi, M. ; Naritake, I. ; Kawamoto, H. ; Iizuka, T. ; Yamamoto, T. ; Kishi, S.

Author_Institution

ULSI Device Dev. Div., NEC Corp., Kanagawa, Japan

fYear

2001

fDate

2-5 Dec. 2001

Abstract

We have developed a 0.13 /spl mu/m embedded DRAM technology, which targets high-speed and low-voltage operation, with logic performance fully compatible with 0.13 /spl mu/m pure logic. Parasitics (resistance, capacitance) of the DRAM macro limit its performances due to RC delay and IR drop. The parasitics of the new DRAM have been successfully minimized by employing the Full Metal embedded DRAM (FMD) technology which consists of a Metal-Insulator-Metal (MIM) capacitor with metal contact, and a newly developed low resistivity bitline. The results of performance simulation using a 16 Mbit DRAM macro show 1.2 V, 450 MHz of high-performance random access operation.

Keywords

DRAM chips; MIM devices; circuit simulation; embedded systems; high-speed integrated circuits; integrated circuit design; low-power electronics; 0.13 micron; 1.2 V; 16 Mbit; 450 MHz; DRAM macro; DRAM parasitics minimization; IR drop; MIM capacitor; RC delay; full metal embedded DRAM technology; high-performance random access operation; high-speed low-voltage operation; logic performance; low resistivity bitline; metal contact; performance simulation; Conductivity; Contact resistance; Logic design; Logic devices; MIM capacitors; Metal-insulator structures; Parasitic capacitance; Random access memory; Tin; Ultra large scale integration;

fLanguage

English

Publisher

ieee

Conference_Titel

Electron Devices Meeting, 2001. IEDM '01. Technical Digest. International

Conference_Location

Washington, DC, USA

Print_ISBN

0-7803-7050-3

Type

conf

DOI

10.1109/IEDM.2001.979522

Filename

979522