Capacitance enhancement techniques for sub-100 nm trench DRAMs

Essential techniques that allow further scaling of trench DRAMs beyond 100 nm have been developed. Al/sub 2/O/sub 3/ was implemented as a high-k node dielectric in silicon-insulator-silicon trench capacitors. Al/sub 2/O/sub 3/ films were deposited by ALD with excellent step coverage at aspect ratios of up to AR/spl ap/60. Even after thermal stressing at 1050/spl deg/C an effective oxide thickness (=capacitance equivalent thickness) of t/sub ox/=3.6 nm and a leakage current of well below 1 fA/cell were obtained. Both selective and non-selective HSG Si was formed inside high-aspect ratio straight and bottled trenches. On fully integrated 0.17 /spl mu/m trench DRAMs, a storage capacitance of 45 fF/cell with acceptable leakage current was achieved. Both the aluminum oxide node dielectric and the HSG silicon have thus been proven to withstand the high thermal budget required for integration into trench DRAMs. In addition, a silicon etch process was developed that allows trench aspect ratios of AR/spl ap/60 at critical dimensions of CD=80 nm.