Propagation of Transients Along Sensitizable Paths

Transient faults have become increasingly observable in combinational logic. This is due to the weakening of some inherent protective mechanisms that logic traditionally holds against such flawed spurious events. One of the aforementioned mechanisms relates to the propagation of transient faults along sensitizable paths. Existing literature that relies on logic simulation under estimates the number of sensitizable paths per circuit. This leads to inconclusive and overly optimistic results when a worst-case analysis is required. In this paper, we present a zero-suppressed binary decision diagram (ZBDD) centered framework, for a complete consideration of all potentially sensitizable paths per circuit. The proposed method is validated in logic paths by evaluating worst-case transient-wave electrical characteristics, such as maximum duration and corresponding amplitude at the circuit outputs.