A 108-GHz Retimer Based on 1.8V QUASI-ECL MOS-HBT SiGe BiCMOS Logic

Author

Yingying Fu ; Voinigescu, S.P.

Author_Institution

Dept. of Electr. & Comput. Eng., Univ. of Toronto, Toronto, ON, Canada

fYear

2013

fDate

13-16 Oct. 2013

Firstpage

1

Lastpage

4

Abstract

This paper describes the first full-rate retimer operating with clock frequencies above 100- GHz. The circuit includes a digitally-controlled equalizer with over 30 dB of peaking control at 55- 60GHz, a 108-GHz flip-flop, and a DC- to-108 GHz clock amplifier. It consumes 540 mW from a 1.8V supply corresponding to an energy efficiency of 5pJ/bit. Equalization was demonstrated over 6m of coaxial cable at 40 Gb/s and 36 Gb/s with full-rate, 2x, and 3x oversampling clocks at 80 GHz and 108 GHz, respectively, and at 75 Gb/s with 75-GHz clock between two probe stations using wafer probes and a 3-m long coaxial cable.

Keywords

BiCMOS logic circuits; Ge-Si alloys; bipolar MIMIC; coaxial cables; emitter-coupled logic; equalisers; flip-flops; heterojunction bipolar transistors; millimetre wave amplifiers; millimetre wave bipolar transistors; semiconductor materials; SiGe; bit rate 36 Gbit/s; bit rate 40 Gbit/s; bit rate 75 Gbit/s; clock amplifier; clock frequency; coaxial cable; digitally-controlled equalizer; energy efficiency; first full-rate retimer; flip-flop; frequency 0 GHz to 108 GHz; power 540 mW; probe stations; quasiECL MOS-HBT BiCMOS logic; size 3 m; voltage 1.8 V; wafer probes; BiCMOS integrated circuits; Clocks; Coaxial cables; Equalizers; Flip-flops; Generators; Silicon germanium;

fLanguage

English

Publisher

ieee

Conference_Titel

Compound Semiconductor Integrated Circuit Symposium (CSICS), 2013 IEEE

Conference_Location

Monterey, CA

Type

conf

DOI

10.1109/CSICS.2013.6659185

Filename

6659185