Energy delay optimization methodology for current-mode signaling for on-chip interconnects

Current mode (CM) scheme provides suitable alternative for the high speed on-chip interconnect signaling. This paper presents a energy-delay optimization methodology for the current-mode (CM) signaling scheme. Optimization for the CM circuits for on-chip interconnects requires a joint optimization of driver and receiver device sizes, as their parameters which affect the energy-delay performance depend on each other. The methodology will be validated using the SPICE simulations. It will be shown that when dealing with the receiver termination sizing, the optimal size is determined by the voltage swing required by the noise margin.