DocumentCode
2169754
Title
High Density MTP Logic NVM for Power Management Applications
Author
Roizin, Yakov ; Pikhay, Evgeny ; Dayan, Vladislav ; Heiman, Alexey
Author_Institution
Tower Semicond. Ltd., Migdal HaEmek
fYear
2009
fDate
10-14 May 2009
Firstpage
1
Lastpage
2
Abstract
We report a no mask adders embedded NVM (Y-Flash) having a record cell area which is suited for power management (PM) applications. The memory cell is a self- aligned asymmetric MOS transistor with drain capacitive coupling to the floating gate (FG) through a three- dimensional extension structure. Operation of the novel memory cell, array organization, design of NVM modules and Y-Flash reliability are addressed.
Keywords
MOSFET; flash memories; reliability; Y-Flash read-disturb free memory cell; array organization; drain capacitive coupling; embedded NVM; floating gate; high density MTP logic NVM; power management; reliability; self-aligned asymmetric MOS transistor; three- dimensional extension structure; Capacitance; Contacts; Electrons; Energy management; Implants; Kinetic theory; Logic; Nonvolatile memory; Poles and towers; Voltage;
fLanguage
English
Publisher
ieee
Conference_Titel
Memory Workshop, 2009. IMW '09. IEEE International
Conference_Location
Monterey, CA
Print_ISBN
978-1-4244-3762-7
Type
conf
DOI
10.1109/IMW.2009.5090593
Filename
5090593
Link To Document