DocumentCode
2169855
Title
Optimized design of parallel prefix Ling adder
Author
Wang, Dayu ; Cui, Xiaoping ; Wang, Xiaojing
Author_Institution
Coll. of Electron. & Inf. Eng., Univ. of Aeronaut. & Astronaut., Nanjing, China
fYear
2011
fDate
9-11 Sept. 2011
Firstpage
941
Lastpage
944
Abstract
Parallel-prefix computation provides a highly efficient solution to binary addition problem. This paper proposes an advanced design based on parallel-prefix Ling adder. In order to further improve the Ling adder´s performance, the preprocessing block and carry propagation block are all optimized to reduce the delay path for sum generation. Experimental results indicate that the proposed adder has an improvement of 21 percent time delay and 25 percent area compared to the traditional Ling adders.
Keywords
adders; carry logic; logic design; optimisation; binary addition problem; carry propagation block; design optimisation; parallel prefix Ling adder; parallel-prefix computation; preprocessing block; sum generation; Adders; Delay; Educational institutions; Equations; Logic gates; Mathematical model; Very large scale integration; Ling adder; VLSI design; logic optimization; parallel-prefix algorithm;
fLanguage
English
Publisher
ieee
Conference_Titel
Electronics, Communications and Control (ICECC), 2011 International Conference on
Conference_Location
Ningbo
Print_ISBN
978-1-4577-0320-1
Type
conf
DOI
10.1109/ICECC.2011.6066361
Filename
6066361
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