Low temperature Si layer splitting

Wafer bonding opens up new design possibilities for the fabrication of various single crystalline semiconductor on insulator (SOI) materials. SOI has been realized by layer splitting (“smart-cut”). However, except in the cases where only a small difference in the thermal expansion coefficients between the Si and the substrates is present, other SOI material combinations usually suffer from excessive thermal stresses due to thermal mismatch between the Si and the dissimilar substrates during annealing before layer splitting. For SOQ (Si on Quartz), at room temperature the thermal expansion coefficient of Si is 2.56×10^-6/°C while that of synthetic quartz is only 0.5×10^-6/°C. A bonded 4" standard Si/quartz pair (both of ~525 μm in thickness), will typically crack at ~180°C. Since the splitting temperature in the smart-cut process exceeds 500°C, the Si wafer in the Si/quartz pair has to be thinned down sufficiently (<150 μm) to avoid cracking of the bonded pair during the Si layer splitting. However, a main advantage offered by the smart cut method is lost, namely that extensive lapping and etching to remove most of the substrate is avoided and the substrate from which the Si layer is transferred can be reused. In order to preserve these advantages a smarter-cut approach which employes a low temperature Si layer splitting technology is described