Key considerations given to the design of a next generation multi-core communications platform

Author

Pham, Dac C.

Author_Institution

Freescale Semicond., Austin, TX

fYear

2008

fDate

2-4 June 2008

Firstpage

253

Lastpage

256

Abstract

Multi-core SoC created great opportunities to increase overall system performance while keeping the power in check but also created many design challenges that designers must now overcome. The challenge of doubling performance every two years used to drive superscalar design with more functional units running concurrently or deeper pipeline racing for highest frequency at the cost of higher power. However, this ever increasing application performance requirement can no longer be sustained without leveraging multi-core and on-demand acceleration. The paper presents the design considerations for the next generation multi-core communications platform.

Keywords

integrated circuit design; integrated circuit interconnections; system-on-chip; memory hierarchy; multi- operating system; multi-core SoC; multi-core communications platform; on-demand acceleration; system bandwidth; virtualization technology; Acceleration; Bandwidth; Communication system control; Costs; Fabrics; Frequency; Pipelines; Process control; System performance; Yarn; AMP; CoreNet; DVFS; Networking; Power Architecture™; SMP; SOC; SOI; VID; cache; coherency fabric; hypervisor; memory hierarchy; multi-core; multioperating system; on-demand acceleration; scale out; scale up; security; system bandwidth; system integration; virtualization technology;

fLanguage

English

Publisher

ieee

Conference_Titel

Integrated Circuit Design and Technology and Tutorial, 2008. ICICDT 2008. IEEE International Conference on

Conference_Location

Austin, TX

Print_ISBN

978-1-4244-1810-7

Electronic_ISBN

978-1-4244-1811-4

Type

conf

DOI

10.1109/ICICDT.2008.4567289

Filename

4567289