• DocumentCode
    2170142
  • Title

    On the performance of a multi-threaded RISC architecture

  • Author

    Lindsay, Scott K. ; Preiss, Bruno R.

  • Author_Institution
    Dept. of Electr. & Comput. Eng., Waterloo Univ., Ont., Canada
  • fYear
    1993
  • fDate
    14-17 Sep 1993
  • Firstpage
    369
  • Abstract
    Multi-threading is a form of parallel processing in which the processor contains several independent contexts which share a single execution pipeline. We propose a new multi-threaded architecture which differs from previous architectures in that context switches are performed only when the running program cannot execute an instruction in the next cycle. We argue that this strategy can improve pipeline utilization in environments which do not have a large enough number of processes to fully utilize earlier multi-threaded machines
  • Keywords
    parallel architectures; performance evaluation; reduced instruction set computing; RISC architecture; context switches; multi-threaded RISC architecture; multi-threaded architecture; parallel processing; pipeline utilization; Delay; Hardware; Hazards; Memory architecture; Parallel processing; Pipelines; Reduced instruction set computing; Switches; Throughput; Yarn;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    Electrical and Computer Engineering, 1993. Canadian Conference on
  • Conference_Location
    Vancouver, BC
  • Print_ISBN
    0-7803-2416-1
  • Type

    conf

  • DOI
    10.1109/CCECE.1993.332333
  • Filename
    332333