TTA processor design for FPFSD-MIMO detector

The research of terminal baseband processing reconfiguration has become the trend of software-defined radio (SDR) which achieves flexibility in an environment with different standards. Transport triggered architecture (TTA) is an ideal processor template for ASIP with customized datapath but without the inflexibility and design cost of fixed function hardware accelerators. This paper mainly designs a universal processor based on Fully Parallel Fixed Complexity Sphere Decoder (FPFSD) algorithm which can be implemented in parallel on TTA. The processor is enhanced with QR and PED special function units (SFU) to accommodate different antenna configurations. The flexibility of ASIPs leaves the approach as an interesting topic for further development.