Implementation of a digital down converter using graphics processing unit

This paper presents a DDC (digital down converter) on NVIDA 580 GTX, which consists of a DDS (direct digital synthesizer), a CIC (cascade integrator comb) decimation filter and a FIR (finite impulse response) filter. The decimating factor of the CIC decimation filter can be arbitrary positive integer and the major concern is concentrated on how to drive it to work well while the decimating factor varies. In our strategy, the problem is ranged into two cases according to whether or not the decimating factor is smaller than 128. Then, we provide suitable method to deal with data in each case. Additionally, we present different ways to construct a root raised cosine filter with 4 times oversampling on GPU (graphics process unit). Through flexible threads assignment and efficient scheduling strategy, the GPU-based DDC is implemented significantly. We evaluate the performance of the designed DDC with respect to its counterpart based on CPU (central processing unit) developed in the C language. Experimental results demonstrate that the DDC shows significant improvements on GPU and achieves a speedup of 387 times.