• DocumentCode
    2171427
  • Title

    Delay test effectiveness evaluation of LSSD-Based VLSI logic circuits

  • Author

    Wu, David M. ; Radke, Charles E.

  • Author_Institution
    IBM East Fishkill
  • fYear
    1991
  • fDate
    21-21 June 1991
  • Firstpage
    291
  • Lastpage
    295
  • Keywords
    Circuit testing; Delay effects; Logic circuits; Logic testing; Materials testing; Permission; System testing; Test pattern generators; Timing; Very large scale integration;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    Design Automation Conference, 1991. 28th ACM/IEEE
  • Conference_Location
    IEEE
  • Print_ISBN
    0-89791-395-7
  • Type

    conf

  • Filename
    979731
    • Link To Document
    https://search.isc.ac/dl/search/defaultta.aspx?DTC=49&DC=2171427