P2Lib: process-portable library and its generation system

Author

Onodera, Hidetoshi ; Hirata, Akio ; Kitamura, Teruo ; Tamaru, Keikichi

Author_Institution

Dept. of Electron. & Commun., Kyoto Univ., Japan

fYear

1997

fDate

5-8 May 1997

Firstpage

341

Lastpage

344

Abstract

This paper describes a process-portable library and its generation system called P2Lib. From technology parameters which characterize a fabrication process, P2Lib generates a complete set of standard cell libraries for logic synthesis, logic simulation, and layout synthesis. A distinctive feature of P2Lib is the rapid characterization of timing and power dissipation by an analytic-oriented method, as well as the accurate characterization by circuit simulation. A designer can quickly create a library under various operating conditions and process specifications, so that he can examine his design with CAD tools. The quality of generated libraries (layout and timing) are discussed and a design example with P2Lib is presented

Keywords

application specific integrated circuits; cellular arrays; circuit analysis computing; circuit layout CAD; digital simulation; logic CAD; logic arrays; timing; CAD tools; P2Lib; analytic-oriented method; circuit simulation; fabrication process; generation system; layout synthesis; logic simulation; logic synthesis; power dissipation; process specifications; process-portable library; standard cell libraries; timing; Character generation; Circuit simulation; Circuit synthesis; Circuit testing; Design automation; Fabrication; Libraries; Logic; Power generation; Timing;

fLanguage

English

Publisher

ieee

Conference_Titel

Custom Integrated Circuits Conference, 1997., Proceedings of the IEEE 1997

Conference_Location

Santa Clara, CA

Print_ISBN

0-7803-3669-0

Type

conf

DOI

10.1109/CICC.1997.606643

Filename

606643