Clock generation using delay lock loop with dual control for PET/CT

Delay locked loop (DLL) has emerged as a viable alternative to the traditional oscillator based phase locked loops. With its first order loop characteristics, a DLL is both easier to stabilize and has no jitter accumulation. This paper describes the design consideration and techniques to achieve high accuracy in a wide range of applications where power consumption issue and false locking can be avoided. The proposed DLL have been used for positron emission tomography/computed tomography (PET/CT) and it has two control voltages, which controls the delay element of the voltage controlled delay line, thereby the jitter is reduced. This circuitry is free from false lock and it has low phase sensitive error. Static D flip flop is used to reduce the power. DLL is used in medical applications and it operates at 1GHz.