DocumentCode
2175115
Title
A universal asynchronous receiver transmitter design
Author
Chun-zhi, He ; Yin-shui, Xia ; Lun-yao, Wang
Author_Institution
Inst. of Circuits & Syst., Ningbo Univ., Ningbo, China
fYear
2011
fDate
9-11 Sept. 2011
Firstpage
691
Lastpage
694
Abstract
In this paper, a UART design is proposed. The design has an auto-tuning baud rate generator. For achieving the speed matching of the processor and UART interface, it takes asynchronous FIFOs as buffers to realize data exchange between UART and external devices. The whole design is functionally verified using ModelSim SE 6.0, and synthesized and optimized by Synplicity´s Synplify Premier 9.6.2.
Keywords
computer interfaces; data communication equipment; ModelSim SE 6.0; Synplify Premier 9.6.2; UART interface; auto-tuning baud rate generator; data exchange; speed matching; universal asynchronous receiver transmitter; Clocks; Generators; IP networks; Image edge detection; Receivers; Synchronization; Transmitters; UART; asynchronous FIFO; auto-tuning baud rate generator; parameterized;
fLanguage
English
Publisher
ieee
Conference_Titel
Electronics, Communications and Control (ICECC), 2011 International Conference on
Conference_Location
Ningbo
Print_ISBN
978-1-4577-0320-1
Type
conf
DOI
10.1109/ICECC.2011.6066542
Filename
6066542
Link To Document