A new SRAM cell design using 0.35 μm CMOS/SIMOX technology

Author

Kumagai, Kouichi ; Yamada, Takashi ; Iwaki, Hiroaki ; Nakamura, Hiroyuki ; Onishi, Hideaki ; Matsubara, Yoshihisa ; Imai, Kiyotaka ; Kurosawa, Susumu

Author_Institution

ULSI Device Dev. Lab., NEC Corp., Sagamihara, Japan

fYear

1997

fDate

6-9 Oct 1997

Firstpage

174

Lastpage

175

Abstract

In SOI/CMOS devices, it is known that the integration density and the circuit performance can be improved using a layout of abutted n⁺ and p⁺ drain regions. Utilizing these advantages in the SOI technology, we have designed a new 6-T memory cell and have developed a 128 Kb synchronous SRAM macro (SOI-SRAM) by 0.35 μm CMOS/SIMOX technology. The SOI-SRAM performance is compared with the reference SRAM macro (REF-SRAM) which is designed with the bulk CMOS memory cell layout

Keywords

CMOS memory circuits; SIMOX; SRAM chips; cellular arrays; integrated circuit design; 0.35 micron; 128 Kbit; 6-T memory cell; CMOS/SIMOX technology; SRAM cell design; abutted n⁺/p⁺ drain regions; integration density; reference SRAM macro; synchronous SRAM macro; CMOS process; CMOS technology; Circuit optimization; Delay effects; Electron devices; Equivalent circuits; Meetings; Process design; Random access memory; Testing;

fLanguage

English

Publisher

ieee

Conference_Titel

SOI Conference, 1997. Proceedings., 1997 IEEE International

Conference_Location

Fish Camp, CA

ISSN

1078-621X

Print_ISBN

0-7803-3938-X

Type

conf

DOI

10.1109/SOI.1997.634989

Filename

634989

Link To Document

https://search.isc.ac/dl/search/defaultta.aspx?DTC=49&DC=2175856