Field programmable gate array based reconfigurable preprocessor

Programmable preprocessing solutions are often unable to meet the required performance. Custom hardware implementations of preprocessors, however, are seldom reusable, flexible or quickly realized. The Configurable Hardware Algorithm Mappable Preprocessor (CHAMP) technology is a solution to these problems. Developments in field programmable gate array (FPGA) hardware and software have made a reconfigurable preprocessor with custom hardware performance but generic hardware flexibility possible. The key advancements are larger, faster RAM and electrically erasable devices, routers with deadline timers, and synthesis tools with user definable macros. Ongoing work will make reconfigurable preprocessors more powerful. The present CHAMP implementation is based on Xilinx FPGAs. Its architecture consists of multiple reconfigurable processing elements connected through both a ring network and a global crossbar network. It is packaged as a VME 6U×160 slave board with two high speed reconfigurable parallel interfaces. To allow development at the algorithm level while retaining preprocessor performance, off-the-shelf development tools have been integrated with a custom library of macros as part of CHAMP design. As a verification of the technology, an advanced IRMW application was mapped onto the CHAMP architecture achieving greater than 1 BOPS of real time throughput while utilizing 75% of the CHAMP board´s processing resources