DocumentCode
2178721
Title
Variable-latency design by function speculation
Author
ñeres, D. Ba ; Cortadella, J. ; Kishinevsky, M.
Author_Institution
Univ. Oberta de Catalunya, Barcelona
fYear
2009
fDate
20-24 April 2009
Firstpage
1704
Lastpage
1709
Abstract
Variable-latency designs may improve the performance of those circuits in which the worst-case delay paths are infrequently activated. Telescopic units emerged as a scheme to automatically synthesize variable-latency circuits. In this paper, a novel approach is proposed that brings three main contributions with regard to the methods used for telescopic units: first, no multi-cycle timing analysis is required to ensure the correctness of the circuit; second, the method can be applied to large circuits; third, the circuit can be optimized for the most frequent input patterns. The approach is based on finding approximations of critical nodes in the netlist that substitute the exact behavior. Two cycles are required when the approximations are not correct. These approximations can be obtained by the simulation of traces applied to the circuit. Experimental results on selected examples show a tangible speed-up (15%) with a small area overhead (3%).
Keywords
combinational circuits; logic design; network synthesis; combinatorial circuits; critical node approximations; function speculation; telescopic units; variable-latency circuit sysnthesis; variable-latency design; Adders; Arithmetic; Circuit synthesis; Clocks; Delay; Error correction; Optical design; Pattern analysis; Signal synthesis; Timing;
fLanguage
English
Publisher
ieee
Conference_Titel
Design, Automation & Test in Europe Conference & Exhibition, 2009. DATE '09.
Conference_Location
Nice
ISSN
1530-1591
Print_ISBN
978-1-4244-3781-8
Type
conf
DOI
10.1109/DATE.2009.5090937
Filename
5090937
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