An Increased Throughput FPGA Design of the JPEG2000 Binary Arithmetic Decoder

As digital imaging techniques continue to advance, new image compression standards are needed to keep the transmission time and storage space low for increasing image sizes. The Joint Photographic Expert Group (JPEG) fulfilled this need with the ratification of the JPEG2000 standard in December of 2000. JPEG2000 adds many features to image compression technology but also increases the computational complexity of traditional encoders. To mitigate the added computational complexity, the JPEG2000 algorithm allows processing parts in parallel, increasing the benefits of implementing the algorithm in application specific integrated circuits (ASICs) or field programmable gate arrays (FPGAs). A flexible FPGA implementation of the JPEG2000 binary arithmetic decoder, the core component of the JPEG2000 decoding algorithm, is presented in this paper. The proposed JPEG2000 binary arithmetic decoder reduces the amount of resources used on the FPGA allowing 17% more entropy block decoders to fit on chip and consequently increasing the throughput by 35% beyond previous designs.