Fault characterization of resistive shorts using a piecewise-linear circuit technique

Resistive shorts are the most common physical faults seen in CMOS circuits. The prediction of their fault signatures, generally by simulation, is prerequisite to dictionary-based fault diagnosis. For cell-synthesized CMOS circuits, a mixed-level approach to fault simulation needs detailed information from fault characterization of logic gates. Due to the inherent complexity of circuit behavior caused by some resistive shorts, electrical-level simulation may be required to obtain electrical data, which often gives rise to excessive computation. In this paper, a piecewise-linear circuit technique is rediscovered for its application to fault characterization of resistive shorts in CMOS logic gates. This technique formulates a faulty circuit as a parametric linear complementarity problem. A procedure centering on complementary pivoting is adapted to solve the problem. The promise of the methodology is justified by example circuits. The results, when compared to SPICE simulation, show a trade-off between numerical accuracy and computational time