A concurrent hardware software management scheme for memory hierarchies

In this paper, we propose to reduce execution time and to gain predictability by making use of a concurrent hardware software scheme for memory hierarchies. Making use of memory hierarchies will allow reducing memory access time while concurrency will relax memory bandwidth resource constraint. The software part of the scheme makes a static analysis of the real time application and generates a file containing special controller instructions. These instructions are generated and scheduled using artificial intelligence optimization techniques so to assure an optimal concurrent management scheme of the memory hierarchy. The hardware part is composed by specially designed memory controllers which are connected to a dedicated bus which allows access to all the memory hierarchy levels. These controllers will execute the instructions associated to the application concurrently with the execution of the application on the microprocessor. Bus contention is avoided between the microprocessor executing the real time application and the controllers on the dedicated bus due to the good scheduling generated at compile time