A ±1.5 V CMOS four-quadrant analogue multiplier using 3 GHz analogue squaring circuits

Author

Li, Simon Cimin ; Lin, Kaung-Long

Author_Institution

Adv. Technol. & Integrated Lab., Nat. Yunlin Univ. of Sci. & Technol., Taiwan, China

Volume

2

fYear

1998

fDate

31 May-3 Jun 1998

Firstpage

347

Abstract

A CMOS four-quadrant analog multiplier using the MOS transistors operated in triode region is proposed. The multiplier is basically constructed by voltage substractors for two differential inputs, and two 3 GHz analog squarers for multiplication. Simulation results are given to verify the theoretical analysis. The multiplier has a nonlinearity error less than 1% over ±1.5 V input range. The circuit provides a -3 dB bandwidth higher than 1.2 GHz and exhibits a THD lower than 4% with a 1.5 V peak-to-peak input voltage, which dissipating 249 μW. The second-order effects including mismatch effects are discussed. The proposed circuit will be useful in analog RF signal-processing applications

Keywords

CMOS analogue integrated circuits; UHF integrated circuits; analogue multipliers; 1.2 GHz; 1.5 V; 3 GHz; CMOS four-quadrant analogue multiplier; MOS transistor; THD; analog RF signal processing; analogue squaring circuit; bandwidth; mismatch effects; nonlinearity error; second-order effects; triode region; voltage substractor; Bipolar integrated circuits; CMOS analog integrated circuits; CMOS technology; Circuit simulation; Dynamic range; Frequency; Integrated circuit technology; MOS devices; MOSFETs; Voltage;

fLanguage

English

Publisher

ieee

Conference_Titel

Circuits and Systems, 1998. ISCAS '98. Proceedings of the 1998 IEEE International Symposium on

Conference_Location

Monterey, CA

Print_ISBN

0-7803-4455-3

Type

conf

DOI

10.1109/ISCAS.1998.706942

Filename

706942