DocumentCode
2182562
Title
Process development of multi-layer stacked chip module
Author
Ma, Shenglin ; Sun, Xin ; Zhu, Yunhui ; Kang, Wenping ; Cui, Qinghu ; Miao, Min ; Chen, Jin ; Jin, Yufeng
Author_Institution
Nat. Key Lab. on Micro/Nano Fabrication Technol., Peking Univ., Beijing, China
fYear
2011
fDate
8-11 Aug. 2011
Firstpage
1
Lastpage
3
Abstract
In this paper, at first electroplating of copper and tin is optimized to fabricate micro-bump. Chip-to-chip bonding process is developed. Then, a temporary bonding process is developed and verified by experiment. And finally, a process for manufacturing multiple layer stacked chip module is designed and prototype of a 4 layer stacked chip module is fabricated successfully.
Keywords
copper alloys; electroplating; integrated circuit metallisation; integrated circuit packaging; three-dimensional integrated circuits; tin alloys; Cu-Sn; chip-to-chip bonding process; electroplating; multilayer stacked chip module; multiple layer stacked chip module; Bonding; Copper; Packaging; Silicon; Stacking; Through-silicon vias; Tin;
fLanguage
English
Publisher
ieee
Conference_Titel
Electronic Packaging Technology and High Density Packaging (ICEPT-HDP), 2011 12th International Conference on
Conference_Location
Shanghai
Print_ISBN
978-1-4577-1770-3
Electronic_ISBN
978-1-4577-1768-0
Type
conf
DOI
10.1109/ICEPT.2011.6066802
Filename
6066802
Link To Document