Variable code length soft-output decoder of polar codes

Hardware implementation of a soft-output polar code decoder that can operate with variable code length and code rate is presented in this paper. The proposed architecture combines the last two clock cycles at the final-stage processing elements to generate efficient soft-output polar decoding results. Compared with the original successive cancellation (SC) decoding design, the proposed soft-output decoding architecture spends almost the same clock cycles. The proposed decoder is designed using TSMC 90 nm GUTM CMOS technology, and the fabricated chip can run at 250 MHz and requires approximately 263K gates. Furthermore, its function was also validated using FPGA, which can serve as a reference design before the silicon implementation of the proposed soft-output polar code decoding architecture.