Comprehensive design of a high frequency PLL synthesizer for ZigBee application

Time-to-market demands shorter design period of applied semiconductor devices. For this reason the iteration steps, the simulation time and repetitions have to be minimized along the design flow. In this paper a new design method of a phase locked loop (PLL) frequency synthesizer and its complete design flow is introduced. This synthesizer is designed mainly for ZigBee application. In this case the top-down design methodology was used. At higher hierarchy levels the Verilog-AMS hardware description language and various Matlab tools were applied. This analogue system will have to be realized on 0.35mum CMOS technology, so the complete layout has to be designed as well. The work has been focused on the main critical element of the PLL circuit, therefore two different types of a voltage controlled oscillator (VCO) blocks were realized. The carrier frequency is around 2.4 GHz during transmission according to the ZigBee standard, thus the VCOs were designed for operating on this frequency. In this paper, the mixed-signal simulation results of the entire system will be introduced, as well