Statistical Model for Logic Errors in CMOS Digital Circuits for Reliability-Driven Design Flow

Author

Abbas, Mohamed ; Ikeda, Makoto ; Asada, Kunihiro

Author_Institution

Dept. of Electron. Eng., Tokyo Univ.

fYear

2006

fDate

18-21 April 2006

Firstpage

145

Lastpage

146

Abstract

In this paper, we present a methodology to evaluate the noise-induced logic error probability in a given CMOS digital design. The logic error probability is modeled in terms of the operating supply voltage, transistor threshold voltage, input static probabilities, circuit configuration and noise level. At this stage of the work, the model is used to locate the weak-nodes against the noise within a design. The model is tested by comparing the results with the transistor-level simulation at specific noise levels. The comparison shows that the model results fit well with the simulation achieving speedup factor of more than 1000 times over the simulation tool. The simulation results have been obtained by using HSPICE, assuming 0.18mum CMOS technology

Keywords

CMOS logic circuits; electromagnetic interference; integrated circuit modelling; integrated circuit reliability; logic testing; statistical analysis; 0.18 micron; CMOS digital circuits; CMOS digital design; logic error probability; noise-induced logic error; reliability-driven design flow; statistical model; transistor-level simulation; CMOS digital integrated circuits; CMOS logic circuits; CMOS technology; Circuit noise; Digital circuits; Error probability; Logic design; Noise level; Semiconductor device modeling; Threshold voltage;

fLanguage

English

Publisher

ieee

Conference_Titel

Design and Diagnostics of Electronic Circuits and systems, 2006 IEEE

Conference_Location

Prague

Print_ISBN

1-4244-0185-2

Type

conf

DOI

10.1109/DDECS.2006.1649597

Filename

1649597