Fast on-chip delay estimation for cell-based emitter coupled logic

An effort was made to produce fast, but accurate, estimates of best and worst-case delay for on-chip emitter-coupled logic (ECL) nets. The effort consisted of two major parts: (1) macromodeling of ECL logic gates acting as both sources and loads; and (2) delay estimation for individual nets using the gate macromodel parameters and RC tree models for metal interconnect. Both of these functions have been extensively tested on an industrial ECL process and cell (i.e., logic gate) library. It is noted that the success of a macromodeling approach relies on repetitive use of members of a library of modeled cells. A fixed computational cost (several CPU hours per cell) is paid to obtain simplified macromodel parameter values. Resultant timing estimates are typically within 5-10% of SPICE and are obtained roughly three orders of magnitude more quickly than SPICE.<>