A novel VLSI architecture for clustering analysis

Author

Mao-Fu Lai ; Hsieh, Chaur-Heh

Author_Institution

Dept. of Electr. Eng., Chinese Culture Univ., Taipei, Taiwan

fYear

1996

fDate

18-21 Nov 1996

Firstpage

484

Lastpage

487

Abstract

This paper presents a novel VLSI architecture for the squared-error clustering algorithm. The proposed architecture reduces the huge number of processing elements (PEs) required by the other previous architectures. The system uses only local communication between adjacent PEs, and it is modular, regular, and expandable. The VLSI implementation of high speed clustering analysis can be realized with significantly less circuit complexity based on the proposed architecture

Keywords

VLSI; digital signal processing chips; pattern recognition; VLSI; circuit complexity; high speed clustering analysis; modular architecture; processing element array; squared-error clustering algorithm; Added delay; Clocks; Clustering algorithms; Complexity theory; Computer architecture; Counting circuits; Registers; Systolic arrays; Very large scale integration;

fLanguage

English

Publisher

ieee

Conference_Titel

Circuits and Systems, 1996., IEEE Asia Pacific Conference on

Conference_Location

Seoul

Print_ISBN

0-7803-3702-6

Type

conf

DOI

10.1109/APCAS.1996.569319

Filename

569319

Link To Document

https://search.isc.ac/dl/search/defaultta.aspx?DTC=49&DC=2188560