DocumentCode
2188945
Title
Fast Block Mode Decision for H.264/AVC on a Programmable Digital Signal Processor
Author
Lee, Wonchul ; Choi, Hyojin ; Sung, Wonyong
Author_Institution
School of Electrical Engineering, Seoul National University, San 56-1, Shillim-dong, Kwanak-gu, Seoul 151-742 Korea, E-mail: chul@dsp.snu.ac.kr
fYear
2007
fDate
17-19 Oct. 2007
Firstpage
169
Lastpage
174
Abstract
Variable block size motion estimation (ME) is one of the new coding tools for H.264/AVC encoder to enhance the video performance. However, the complexity of the variable block size ME is very high because the motion estimation and rate-distortion optimization need to be performed repeatedly for all the possible block mode combinations. In order to reduce this, we propose a new block mode decision algorithm, which can decide the block mode efficiently without trying all the block modes by using the spatial property of image sequences. The experimental results on a VLIW (Very Long Instruction Word) ¿ SIMD (Single Instruction Multiple Data) programmable digital signal processor (DSP) show that the proposed algorithm can save the CPU clock cycles by 47% for the integer-pel ME and 83% for the sub-pel ME. The video performance degradation in terms of PSNR and bitrates is 0.12 dB and 1.04%, respectively.
Keywords
Automatic voltage control; Clocks; Degradation; Digital signal processing; Digital signal processors; Image sequences; Motion estimation; Rate-distortion; Signal processing algorithms; VLIW; H.264/AVC encoder; VLIW-SIMD digital signal processor; motion estimation; rate-distortion optimization; variable block size;
fLanguage
English
Publisher
ieee
Conference_Titel
Signal Processing Systems, 2007 IEEE Workshop on
Conference_Location
Shanghai, China
ISSN
1520-6130
Print_ISBN
978-1-4244-1222-8
Electronic_ISBN
1520-6130
Type
conf
DOI
10.1109/SIPS.2007.4387539
Filename
4387539
Link To Document