DocumentCode
2190184
Title
A novel 116 dB operational amplifier design using positive feedback
Author
Chakraborty, Subhra ; Pandey, Abhishek ; Nath, Vijay
Author_Institution
Electronics and Communication Engineering, Birla Institute of Technology, Mesra, Ranchi, Jharkhand, India, Pin-835215
fYear
2015
fDate
24-25 Jan. 2015
Firstpage
1
Lastpage
4
Abstract
A gain boosted operational amplifier designed using positive feedback technique is presented in this paper. In this design, a differential output differential amplifier merged with a single output differential amplifier is used so that positive feedback can be applied appropriately. The proposed Op-Amp is designed in 0.18µm CMOS process using gpdk45nm library in Cadence virtuoso analog design environment. The simulation of proposed circuit results in 116.2dB gain, 281MHz UGB, 72 degree phase margin and 620µW power consumption. The Monte Carlo analysis of the circuit indicates that the variation of power supply voltage produces minimal effect on the gain and phase of the circuit.
Keywords
CMOS integrated circuits; Differential amplifiers; Gain; Integrated circuit modeling; MOSFET; Semiconductor device modeling; CMOS Op-Amp; High Gain; Positive Feedback;
fLanguage
English
Publisher
ieee
Conference_Titel
Electrical, Electronics, Signals, Communication and Optimization (EESCO), 2015 International Conference on
Conference_Location
Visakhapatnam, India
Print_ISBN
978-1-4799-7676-8
Type
conf
DOI
10.1109/EESCO.2015.7253640
Filename
7253640
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