Power estimation of sequential circuits using hierarchical colored hardware Petri net modeling

Author

Murugavel, Ashok K. ; Ranganathan, N.

Author_Institution

Dept. of Comput. Sci. & Eng., Univ. of South Florida, Tampa, FL, USA

fYear

2002

fDate

2002

Firstpage

267

Lastpage

270

Abstract

A hierarchical colored hardware Petri net (HCHPN) based model was proposed in (A. K. Murugavel et al, Proc. of Intl. Conf. on VLSI Design, pp. 181-186, 2001) for estimating switching activity in combinational circuits. In this paper, we model sequential circuits as HCHPNs incorporating real delays for both gates and interconnects. Thus, the given sequential circuit is first modeled as a HCHPN and simulated for switching activity estimation in the Petri net domain which leads to better accuracy and faster simulation. Experimental results for ISCAS´89 benchmark circuits show that the proposed HCHPN model yields accuracy on an average within 4.4% of that of PowerMill. The per-pattern simulation time for HCHPNs is about 2.4 times less than that of PowerMill.

Keywords

Petri nets; circuit simulation; combinational circuits; delays; integrated circuit modelling; logic CAD; performance evaluation; sequential circuits; HCHPN based model simulation; Petri net domain; benchmark circuits; combinational circuit switching activity estimation; gate delays; hierarchical colored hardware Petri net modeling; interconnect delays; per-pattem simulation time; sequential circuit power estimation; simulation accuracy; Capacitance; Circuit simulation; Computer science; Delay estimation; Hardware; Integrated circuit interconnections; Logic; Permission; Sequential circuits; Switching circuits;

fLanguage

English

Publisher

ieee

Conference_Titel

Low Power Electronics and Design, 2002. ISLPED '02. Proceedings of the 2002 International Symposium on

Print_ISBN

1-5811-3475-4

Type

conf

DOI

10.1109/LPE.2002.146752

Filename

1029618