Design and implementation of concurrent computing multi processor core architecture with multi UART

Now a days the computer architecture development resources away from the uniprocessor technology to multiprocessor technology. The existed multiprocessor core architecture has faced a problem with thread interdependencies due to lack of internal synchronization of multi-processor. For this purpose the designed concurrent computing multiprocessor core architecture performs both parallel and distributed computations simultaneously. The interdependencies are eliminated by using parallel computations and shared data problems are annihilated by duplicated memories. The main advantage of designed architecture is integrated Multi Universal Asynchronous Receiver and Transmitter (MUART). The Multi Universal Asynchronous Receiver and Transmitter (MUART) to enable the data transmission and reception concurrently on the FPGA. It performs both transmission and reception of data by concurrent computational technique. The area, speed and power of designed architecture are analyzed using Xilinx platform.