SAT: A Stream Architecture Template for Embedded Applications

The increase of embedded applications complexity has demanded hardware more flexible while providing higher performance. Reconfigurable architectures and stream processing have been showed significant progresses in exploiting these applications. This paper presents SAT, a stream architecture template that combines stream processing, clustered-VLIW, multi-core, and hardware reuse to achieve the capability of high performance and high flexibility. In order to enhance the efficiency of the auto-generated circuit, we introduced the idea of parameter and template in SAT. In this paper, we also demonstrated a flow of generating the target system based on SAT. The system is implemented in VerilogHDL, and consists of configurable stream core, RISC core, memory core, IO core, and interconnect core. The diverse stream-based implementation of stream core can be configured easily according to the requirements of applications. The system has also been synthesized into an Altera FPGA to verify resource utilization and performance.