DocumentCode
2192783
Title
Area-power efficient vedic multiplier using compressors
Author
Abhilash, R. ; Raju, I.B.K ; Chary, Gnaneshwara ; Dubey, Sanjay
Author_Institution
Department of ECE, BVRIT, Narsapur, Medak(Dist), Telangana, India
fYear
2015
fDate
24-25 Jan. 2015
Firstpage
1
Lastpage
5
Abstract
Vedic is famous for multiplication data representation. Vedic multiplier algorithm is used to improve the performance efficiency of the complex computations. In this paper, we proposed a novel 4:2 compressor and two 5:2 compressors architecture. In this architecture, we reduced latency and area. The performances of these compressors are evaluated by using Vedic algorithm. Proposed compressor architectures have shown better performance than existing Vedic algorithm based architecture.
Keywords
Adders; Compressors; Computer architecture; Delays; Microprocessors; Multiplexing; Signal processing algorithms; Compressor; Multiplier; Vedic;
fLanguage
English
Publisher
ieee
Conference_Titel
Electrical, Electronics, Signals, Communication and Optimization (EESCO), 2015 International Conference on
Conference_Location
Visakhapatnam, India
Print_ISBN
978-1-4799-7676-8
Type
conf
DOI
10.1109/EESCO.2015.7253747
Filename
7253747
Link To Document