Error correction coding for a serial digital multi-gigabit communication system

This paper presents the analysis used in choosing and designing an error correction coding (ECC) scheme for a wired serial digital multi-gigabit communication system. Background information is provided on multi-gigabit systems, followed by a detailed analysis leading to an ECC design. The analysis consists of determining the transmission channel bandwidth, identifying the significant noise sources, using estimates of E_b/N₀ to determine channel capacity, establishing the relevant characteristics of the source data, and determining for specified random and deterministic jitter levels the probability of a bit error vs. the sampling time point. These analyses are used to develop ECC requirements for the selection and design of the code. A two-error correcting BCH code is selected and specified. The target for implementation of the ECC design is an Altera Stratix GX Field programmable gate array (FPGA). This family of FPGAs contains embedded serial transceivers that can operate at up to 3.125 Gbps. The ECC design in this paper included consideration of the capabilities of an FPGA implementation.