DocumentCode
2197775
Title
Design of a low voltage Phase Locked Loop for clock generation
Author
Venkateswarlu, Mannem ; Sarangam, K
Author_Institution
Dept. of Electronics and Communication Engineering, GITAM University, Hyderabad Campus, India
fYear
2015
fDate
24-25 Jan. 2015
Firstpage
1
Lastpage
6
Abstract
A 1.2V CMOS Phase Locked Loop (PLL) is designed in 0.18µm CMOS technology. The proposed PLL will generate the output clock frequency of 350 MHz with low power consumption. The PLL contains Phase Frequency Detector (PFD), Charge Pump (CP), Loop Filter, Voltage Controlled Oscillator (VCO) and Frequency Divider. These blocks are designed such that they will work under a low voltage supply. The Phase noise is measured as −100dbc/Hz and the power consumption is calculated as 1mW.
Keywords
Charge pumps; Clocks; Detectors; Frequency conversion; Phase frequency detector; Phase locked loops; Voltage-controlled oscillators; Charge Pump; Clock Generation; Damping factor; Loop Bandwidth; Natural frequency; PLL; Phase Frequency Detector; Ring VCO;
fLanguage
English
Publisher
ieee
Conference_Titel
Electrical, Electronics, Signals, Communication and Optimization (EESCO), 2015 International Conference on
Conference_Location
Visakhapatnam, India
Print_ISBN
978-1-4799-7676-8
Type
conf
DOI
10.1109/EESCO.2015.7253946
Filename
7253946
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