High speed Square Root Carry Select Adder using MTCMOS D-Latch in 45nm technology

In the research area of VLSI system design the Adders have always been the fundamental requirements for high performance processors and multi-core devices. On the basis of area, delay and power consumption, different adder circuits are proposed but the trade off between these performance metrics forces to choose the efficient circuits for data path design. This Proposed Structure is based on the Multi-Threshold CMOS (MTCMOS) based D-Latch instead of using Binary to Excess-1(BEC) or (Ripple Carry Adder)RCA for Cin=0. This work has been evaluated for 8-bit Square Root Carry Select Adder (SQRT CSLA) in terms of delay and power in Cadence Virtuoso environment 45nm CMOS process technology in room temperature with supply voltage 1volt. D-Latch based circuit has reduced Delay of 42.21% where as proposed MTCMOS based D-latch based circuits has 50.27% delay minimization as compared to BEC converter based SQRT CSLA. There is 13.94% delay and the 5.70% power have been reduced in MTCMOS D-Latch circuits when compared with the D-Latch based SQRT CSLA.