DocumentCode
2200193
Title
A Novel Low-Power and High-Speed Master-Slave D Flip-Flop
Author
Gao, Hongli ; Qiao, Fei ; Wei, Dingli ; Yang, Huazhong
Author_Institution
Dept. of Electron. Eng., Tsinghua Univ., Beijing
fYear
2006
fDate
14-17 Nov. 2006
Firstpage
1
Lastpage
4
Abstract
A novel low-power and high-speed master-slave D flip-flop (MSDFF) is proposed in this paper. Without clocked inverter on critical path, the flip-flop operation speed has been improved. Employing the pseudo-NAND logic in the slave stage, the flip-flop has a smaller clock capacitance load, which helps to reduce the power consumption. The proposed flip-flop is verified with GSMC 1.5 V-0.15 mum CMOS technology. Compared with the widely used conventional D flip-flop, 48% power-delay-product (PDP) saving can be achieved, and both the power consumption and transition delay performance are better than many other flip-flops
Keywords
flip-flops; logic gates; low-power electronics; 0.15 micron; 1.5 V; CMOS technology; MSDFF; high-speed master-slave D flip-flop; low-power flip-flop; pseudo-NAND logic; Capacitance; Clocks; Costs; Delay; Energy consumption; Flip-flops; Inverters; Master-slave; Power dissipation; Switches;
fLanguage
English
Publisher
ieee
Conference_Titel
TENCON 2006. 2006 IEEE Region 10 Conference
Conference_Location
Hong Kong
Print_ISBN
1-4244-0548-3
Electronic_ISBN
1-4244-0549-1
Type
conf
DOI
10.1109/TENCON.2006.344110
Filename
4142225
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