A model for a reconfigurable fine-grained optoelectronic processor

A model for a dataflow based processor is described in which a program written in a high level language is mapped directly to hardware. The concept is to reconfigure the interconnection network among an array of processing elements (PEs) to match the natural form of a computation, as represented by a dataflow graph. Communication among PEs is handled optically using free-space interconnects. A group of vertical cavity surface emitting lasers (VCSELs) is dedicated to each output port of a PE, which corresponds to an arc in a dataflow graph. Outputs of the VCSELs are imaged through a reconfigurable optical permutation network that redirects beams to their destinations. This combination of optics and electronics may support fine-grained parallelism while balancing time spent in communication with time spent in computation