Multi-level fault injection experiments based on VHDL descriptions: a case study

Author

Leveugle, R. ; Hadjiat, K.

Author_Institution

TIMA Lab., Grenoble, France

fYear

2002

fDate

2002

Firstpage

107

Lastpage

111

Abstract

The probability of transient faults increases with the evolution of technologies. There is a corresponding increased demand for an early analysis of erroneous behaviors. This paper reports on results obtained with SEU-like fault injections in VHDL descriptions of digital circuits. Several circuit description levels are considered, as well as several fault modeling levels. These results show that an analysis performed at a very early stage in the design process can actually give a helpful insight into the response of a circuit when a fault occurs.

Keywords

VLSI; fault simulation; hardware description languages; high level synthesis; integrated circuit testing; logic testing; multivalued logic circuits; radiation hardening (electronics); CAD environment; SEU-like fault injections; VHDL descriptions; VLSI design; dependability analysis; digital circuits; erroneous transitions; fault modeling; multilevel circuits; multilevel fault injection; single bit-flips; state registers; transient faults probability; CMOS technology; Circuit faults; Circuit testing; Computer aided software engineering; Digital circuits; Laboratories; Performance analysis; Process design; Semiconductor device modeling; Space technology;

fLanguage

English

Publisher

ieee

Conference_Titel

On-Line Testing Workshop, 2002. Proceedings of the Eighth IEEE International

Print_ISBN

0-7695-1641-6

Type

conf

DOI

10.1109/OLT.2002.1030192

Filename

1030192