• DocumentCode
    2202990
  • Title

    Some faults need an I/sub ddq/ test

  • Author

    Makar, Samy R. ; McCluskey, Edward J.

  • Author_Institution
    Center for Reliable Comput., Stanford Univ., CA, USA
  • fYear
    1996
  • fDate
    24-25 Oct. 1996
  • Firstpage
    102
  • Lastpage
    103
  • Abstract
    Fault Simulation results of different implementations of 2-1 multiplexers and D-latches are presented. These results show that some faults can only be detected by I/sub ddq/ test. Simulation results also show that the "importance" of I/sub ddq/ as a test method can vary considerably with implementation.
  • Keywords
    CMOS logic circuits; electric current measurement; fault diagnosis; integrated circuit testing; leakage currents; logic testing; D-latches; I/sub ddq/ test; fault simulation; logic circuits; multiplexers; Circuit faults; Circuit simulation; Circuit testing; Current measurement; Delay; Electrical fault detection; Fault detection; Integrated circuit interconnections; Multiplexing; Voltage;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    IDDQ Testing, 1996., IEEE International Workshop on
  • Conference_Location
    Washington, DC, USA
  • Print_ISBN
    0-8186-7655-8
  • Type

    conf

  • DOI
    10.1109/IDDQ.1996.557841
  • Filename
    557841
    • Link To Document
    https://search.isc.ac/dl/search/defaultta.aspx?DTC=49&DC=2202990